k6x8008c2b family revision 2.0 1 cmos sram march 2005 document title 1mx8 bit low power and low voltage cmos static ram revision history revision no. 0.0 0.1 1.0 2.0 remark preliminary preliminary final final history initial draft revised - deleted 44-tsop2-400r package type. - added commercial product. finalized - changed i cc from 10ma to 6ma - changed i cc 1 from 10ma to 7ma - changed i cc 2 from 50ma to 35ma - changed i sb from 3ma to 0.4ma - changed i sb 1 (commercial) from 40 a to 25 a - changed i sb 1 (industrial) from 40 a to 25 a - changed i sb 1 (automotive) from 50 a to 40 a - changed i dr (commercial) from 30 a to 15 a - changed i dr (industrial) from 30 a to 15 a - changed i dr (automotive) from 40 a to 30 a revised - changed i sb 1 of automotive product from 40 a to 100 a - changed i dr of automotive product from 30 a to 80 a - added lead free products draft date october 31, 2002 december 11, 2002 september 16, 2003 march 27. 2005 the attached datasheets are provided by sams ung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to yourquestions about de vice. if you have any questions , please contact the samsung branch offices.
k6x8008c2b family revision 2.0 2 cmos sram march 2005 1mx8 bit low power full cmos static ram general description the k6x8008c2b families are fabricated by samsung s advanced full cmos process technology. the families sup- port various operating temperatur e range for user flexibility of system design. the families al so support low data retention voltage for battery back-up operation with low data retention current. features ? process technology: full cmos ? organization: 1m x8 ? power supply voltage: 4.5~5.5v ? low data retention voltage: 2.0v(min) ? three state output and ttl compatible ? package type: 44-tsop2-400f name function name function cs 1 , cs 2 chip select inputs vcc power oe output enable input vss ground we write enable input a 0 ~a 19 address inputs i/o 1 ~i/o 8 data inputs/outputs nc no connect pro duct family 1. the parameter is measured with 50pf test load. product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2 , max) k6x8008c2b-b commercial(0~70 c) 4.5~5.5v 55 1) /70ns 25 a 35ma 44-tsop2-400f k6x8008c2b-f industrial(-40~85 c) 25 a k6x8008c2b-q automotive(-40~125 c) 100 a samsung electronics co., ltd. reserves the right to change products and specifications without notice. functional block diagram clk gen. row select i/o 1 ~i/o 8 data cont data cont vcc vss precharge circuit. memory array i/o circuit column select pin description we oe cs 1 control logic cs2 row addresses column addresses a4 a3 a2 a1 a0 cs 1 nc nc i/o1 i/o2 vcc vss i/o3 i/o4 nc nc we a19 a18 a17 a16 a5 a6 a7 oe cs2 a8 nc nc i/o8 i/o7 vss vcc i/o6 i/o5 nc nc a9 a10 a11 a12 44-tsop2 forward 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 a15 a14 a13
k6x8008c2b family revision 2.0 3 cmos sram march 2005 product list 1. lf : lead free product commercial products(0~70 c) industrial products(-40~85 c) automotive products(-40~125 c) part name function part name function part name function k6x8008c2b-tb55 k6x8008c2b-tb70 k6x8008c2b-ub55 k6x8008c2b-ub70 44-tsop2-f, 55ns, ll 44-tsop2-f, 70ns, ll 44-tsop2-f, 55ns, ll, lf 44-tsop2-f, 70ns, ll, lf k6x8008c2b-tf55 k6x8008c2b-tf70 k6x8008c2b-uf55 k6x8008c2b-uf70 44-tsop2-f, 55ns, ll 44-tsop2-f, 70ns, ll 44-tsop2-f, 55ns, ll, lf 44-tsop2-f, 70ns, ll, lf k6x8008c2b-tq55 k6x8008c2b-tq70 k6x8008c2b-uq55 k6x8008c2b-uq70 44-tsop2-f, 55ns, l 44-tsop2-f, 70ns, l 44-tsop2-f, 55ns, l, lf 44-tsop2-f, 70ns, l, lf absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent dama ge to the device. functional ope ration should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in , v out -0.5 to v cc +0.5v(max.7.0v) v - voltage on vcc supply relative to vss v cc -0.3 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c- operating temperature t a 0 to 70 c k6x8008c2b-b -40 to 85 c k6x8008c2b-f -40 to 125 c k6x8008c2b-q functional description note: x means don t care. (must be low or high state) cs 1 cs 2 oe we i/o 1~8 mode power h xxx high-z deselected standby x l xx high-z deselected standby l h h h high-z output disabled active l h l h dout read active lh x l din write active
k6x8008c2b family revision 2.0 4 cmos sram march 2005 recommended dc operating conditions 1) note: 1. commercial product: t a =0 to 70 c, otherwise specified. industrial product: t a =-40 to 85 c, otherwise specified. automotive product: t a =-40 to 125 c, otherwise specified. 2. overshoot: v cc +3.0v in case of pulse width 30ns. 3. undershoot: -3.0v in case of pulse width 30ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6x8008c2b family 4.5 5.0 5.5 v ground vss all family 0 0 0 v input high voltage v ih k6x8008c2b family 2.2 - vcc+0.5 2) v input low voltage v il k6x8008c2b family -0.5 3) -0.8v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested. item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 a output leakage current i lo cs 1 =v ih, cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 a operating power supply current i cc i io =0ma, cs 1 =v il, cs 2 =v ih , we =v ih , v in =v ih or v il --6ma average operating current i cc1 cycle time=1 s, 100%duty, i io =0ma, cs 1 0.2v, cs 2 vcc-0.2v, v in 0.2v or v in v cc -0.2v --7ma i cc2 cycle time=min, i io =0ma, 100% duty, cs 1 =v il , cs 2 =v ih, v in =v il or v ih --35ma output low voltage v ol i ol = 2.1ma - - 0.4 v output high voltage v oh i oh = -1.0ma 2.4 - - v standby current(ttl) i sb cs 1 =v ih , cs 2 =v il , other inputs=v ih or v il --0.4ma standby current(cmos) i sb1 other input =0~vcc, 1) cs 1 vcc-0.2v, cs 2 vcc-0.2v (cs 1 con- trolled) or 2) 0v cs 2 0.2v(cs 2 controlled) k6x8008c2b-b - - 25 a k6x8008c2b-f - - 25 k6x8008c2b-q - - 100
k6x8008c2b family revision 2.0 5 cmos sram march 2005 c l 1 ) 1.including scope and jig capacitance ac operating conditions test conditions (test load and input/output reference) input pulse level: 0.8 to 2.4v input rising and falling time: 5ns input and output reference voltage: 1.5v output load(see right): c l =100pf+1ttl c l =50pf+1ttl data retention characteristics 1. cs 1 vcc-0.2v,cs 2 vcc-0.2v(cs 1 controlled) or cs 2 vcc-0.2v(cs 2 controlled). item symbol test condition min typ max unit vcc for data retention v dr cs 1 vcc-0.2v 1) 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 1 vcc-0.2v 1) k6x8008c2b-b -- 15 a k6x8008c2b-f 15 k6x8008c2b-q 80 data retention set-up time t sdr see data retention waveform 0- - ms recovery time t rdr 5- - ac characteristics (v cc =4.5~5.5v, commercial product: t a =0 to 70 c, industrial product: t a =-40 to 85 c, automotive product: t a =-40 to 125 c) parameter list symbol speed bins units 55ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa -55-70ns chip select to output t co -55-70ns output enable to valid output t oe -25-35ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5-5-ns chip disable to high-z output t hz 020025ns output disable to high-z output t ohz 020025ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0-0-ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0-0-ns write to output high-z t whz 020020ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0-0-ns end write to output low-z t ow 5-5-ns
k6x8008c2b family revision 2.0 6 cmos sram march 2005 address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs 1 =oe =v il , cs 2 =we =v ih ) t aa t rc t oh timing waveform of read cycle(2) (we =v ih ) data valid high-z cs 1 address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the o pen circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
k6x8008c2b family revision 2.0 7 cmos sram march 2005 timing waveform of write cycle(2) (cs 1 controlled) address cs 1 t wc t wr(4) t as(3) t dw t dh data valid we data in data out high-z high-z cs 2 t cw(2) t wp(1) t aw timing waveform of write cycle(1) (we controlled) address cs 1 t cw(2) t wr(4) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t wc t aw t as(3)
k6x8008c2b family revision 2.0 8 cmos sram march 2005 data retention wave form cs 1 controlled v cc 4.5v 2.2v v dr cs 1 gnd data retention mode cs 1 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) (cs 2 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low : a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs 1 or we going high t wr2 applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 4.5v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
k6x8008c2b family revision 2.0 9 cmos sram march 2005 unit: millimeters(inches) package dimensions 44 pin thin small outline package type ii (400f) 0.002 #1 0.05 #22 #44 #23 0.35 0.10 0.014 0.004 0.80 0.0315 min. 0.047 1.20 max. 0.741 18.81 max. 18.41 0.10 0.725 0.004 11.76 0.20 0.463 0.008 + 0 . 1 0 - 0 . 0 5 0.50 + 0 . 0 0 4 - 0 . 0 0 2 0 . 1 5 0 . 0 0 6 0.020 10.16 0.400 0.10 0.004 0~8 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 ( ) 0.805 0.032 ( ) max 1.00 0.10 0.039 0.004
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